Zerui Guo
cyrus.guo at wisc.edu
I am Zerui (Cyrus) Guo, a final-year Ph.D. student in computer science at the University of Wisconsin-Madison, advised by Prof. Ming Liu. I expect to graduate in May 2027. Previously, I received my master’s degree from Beihang University and my bachelor’s degree from Beijing University of Posts and Telecommunications.
I build efficient and predictable networked systems through performance modeling, hardware-aware design, and adaptive scheduling and control. My work spans SmartNIC-based storage and performance modeling, CXL memory profiling and pooling, and accelerated application pipelines. Across these systems, I study how to understand hardware bottlenecks, align execution with hardware capabilities, and control contention among shared resources.
Publications
2026
- NSDIBuilding A CSFQ-Inspired Transport for Switched CXL Memory PoolingIn 23rd USENIX Symposium on Networked Systems Design and Implementation (NSDI 26), 2026
2025
- SIGCOMMUnderstanding and Profiling CXL.mem Using PathFinderIn Proceedings of the ACM SIGCOMM 2025 Conference, 2025
- NSDIBuilding Massive MIMO Baseband Processing on a Single-Node SupercomputerIn 22nd USENIX Symposium on Networked Systems Design and Implementation (NSDI 25), 2025
2023
- MICROLogNIC: A High-Level Performance Model for SmartNICsIn Proceedings of 56th IEEE/ACM International Symposium on Microarchitecture, October 2023
- SIGCOMMLEED: A Low-Power, Fast Persistent Key-Value Store on SmartNIC JBOFsIn Proceedings of the ACM SIGCOMM 2023 Conference, September 2023